Because semiconductor integrated circuit devices have been improved in performance and reduced in size, the multilayer-wiring art is an art that is indispensable for manufacturing of such semiconductor integrated circuit devices. For example, to form a wiring layer of a semiconductor integrated circuit, a method is known in which a thin film made of a refractory metal such as an aluminum (Al) alloy or tungsten (W) is formed on an insulating film, then a resist pattern having a shape which is the same as that of a wiring pattern is formed on a wiring thin film in a photolithography step, and then a wiring pattern is formed in a dry etching step by using the resist pattern as a mask. However, as the wiring is made finer, the method using an Al alloy or the like has problems that wiring resistance remarkably increases, and thereby, the wiring delay increases, and the performance of the semiconductor integrated circuit device deteriorates. Particularly, a large problem for advanced logic LSI is its performance deterioration factor.
Therefore, a method (so-called damascene method) has been studied in which a wiring metal using copper (Cu) as a main conductive layer is embedded in a trench formed on an insulating film, and excessive metal outside of the trench is removed by the CMP (Chemical Mechanical Polishing) method, and thereby, a wiring pattern is formed in the trench.
Moreover, the problem of wiring capacity is a factor which causes an operation delay in the semiconductor integrated circuit device in addition to wiring resistance. Improving the integration degree and reducing the size of a semiconductor integrated circuit device are not preferable solutions because, as the inter-wiring dimension is decreased, the inter-wiring capacity is increased, and thus circuit-operation delay is increased. Therefore, a low-permittivity material such as a silicon-oxide film is generally used for an interlayer dielectric film for insulating and wiring from another.
However, the present inventors recognize that the generation of AC noises during circuit operation becomes a problem as the integration degree and operation speed of the semiconductor integrated circuit device are improved, and the operating voltage is lowered. That is, when a fine circuit device performs a high-speed operation at a specified section, a phenomenon locally occurs in that the power-source impedance of the section lowers. This is observed as a local lowering of the power-source voltage which is to be supplied to a circuit. Moreover, because the phenomenon is observed as a temporally fluctuating voltage, it is detected as local AC noises. In the case of a circuit driven at a low voltage, the above AC noises particularly influence the circuit, and they may cause circuit operations to be unstable. Also, when the noises are extreme, they may cause the circuit to malfunction.
The process of connecting a proper capacitive element (power-source stabilizing capacitor) between power-source lines {Vdd and Vss (Vdd>Vss)} in order to prevent the AC noises was considered in the present inventors' studies. Though not a publicly-known art, the following means are studied as specific countermeasures.
When a semiconductor integrated circuit device is a cell-based IC (CBIC: Cell Based Integrated Circuit) according to the standard cell system or the like, a countermeasure is provided of separately forming a capacitive element (MIS capacitive element) for stabilizing the power source in a certain area in the IC by using a gate-insulating film and connecting the capacitive element to a power-source line. That is, as shown in FIG. 34A, a sufficient capacity value can be obtained by separately setting a capacitive cell C, as shown in FIG. 34A, and increasing the gate-electrode length L and width W of an MISFET (Metal Insulator Semiconductor Field Effect Transistor) in the capacitive cell as shown in FIG. 34C.
FIGS. 34A to 34C are illustrations which explain problems of the present invention, FIG. 34A is a plan view of a semiconductor integrated circuit device in which standard cells are formed in an internal area, FIG. 34B is an enlarged plan view of a capacitive cell area, FIG. 34C is an enlarged plan view of a capacitive cell, and FIG. 34D is a sectional view taken along the line d–d′ in FIG. 34C. Thus, a capacitive element is constituted by electrically connecting the power-source line Vdd to the gate electrode of the MISFET in the capacitive cell, thereby using the gate electrode as one electrode of the capacitive element, using a p-well region (potential Vss) and source and drain regions as the other electrode of the capacitive element, and using the gate-insulating film as a dielectric film of the capacitive element. Moreover, a capacitive element is constituted by electrically connecting the power-source line Vss to the gate electrode of a pMISFET, thereby using the gate electrode as one electrode of the capacitive element, using an n-well region (potential Vdd) and source and drain regions as the other electrode of the capacitive element, and using the gate-insulating film as a dielectric film of the capacitive element. This countermeasure has the advantage that a comparatively are stabilizing capacitor can be obtained because a dedicated capacity cell is set in a semiconductor integrated circuit device.
However, because this countermeasure requires a dedicated capacitive element for stabilizing a power source, an excessive area for forming the capacitive element is necessary and thus, the problem is that improvement of the integration density is prevented. Moreover, as shown in FIG. 34B, because the position for forming the capacitive cell C is restricted to a specific position in the chip, the capacitive cell is formed at a position which is separate from an area such as a logical block R generating AC noises, that is, an area requiring a stabilizing capacitor. Therefore, the AC-noise generating position is different from the stabilization-pack forming position, and thereby, it may not be possible to effectively remove noises.
When a semiconductor integrated circuit device is a gate array circuit, a countermeasure is provided of using an unused basic cell as a capacitive element (MIS capacitive element) and connecting the basic cell between power-source lines. That is, as shown in FIG. 35B, the second means uses a countermeasure of using an MISFET constituting the basic cell as a stabilization capacity. FIGS. 35A and 35B are other illustrations which explain problems in the present invention, in which FIG. 35A is a plan view showing a semiconductor integrated circuit device in which a gate array is formed in the internal area, and FIG. 35B is a plan view showing a basic cell of the gate array. In the case in which the semiconductor integrated circuit device uses a gate array system, a capacitive element (MIS capacitive element) which is the same as the capacitive element (MIS capacitive element) shown in FIGS. 34C and 34D is constituted by using an unused basic cell instead of using a dedicated capacitive cell as in the case of the cell based IC (CBIC). According to this countermeasure, because an unused basic cell is used, an excessive area (overhead of area) for a stabilizing capacitor is unnecessary and, therefore, this countermeasure is advantageous for improving the integration degree, though excessive wirings (overhead of wiring) are increased.
However, because this countermeasure uses an existing basic cell as shown in FIG. 35B, a gate-electrode length L is generally small, and it is difficult to obtain a large stabilizing capacitor because the capacity per MOS transistor is small. Because the forming position of a basic cell that can be used as a stabilizing capacitor is restricted to a specific position in a chip, it is not always possible to set the basic cell near an area generating AC noises. Therefore, an AC-noise generating position is different from a stabilizing-capacitor forming position, and it may not be possible to effectively remove noises.
It is an object of the present invention to provide a structure of a semiconductor integrated circuit device and a method of manufacturing a semiconductor integrated circuit device capable of obtaining a large stabilizing capacitor without increasing areas or wirings.
It is another object of the present invention to add a large stabilizing capacitor between power-source lines (Vdd and Vss), reduce AC noises, and improve the operational stability and operational reliability of a semiconductor integrated circuit device.
It is still another object of the present invention to provide an arrangement capable of uniformly arranging stabilizing capacitors in a chip, that is, to provide an arrangement capable of effectively removing local AC noises by the stabilizing capacitors arranged near the portion generating the noises and thereby further improving the stability of a semiconductor integrated circuit device.
The above and other objects and novel features of the present invention will become more apparent from the description of this specification and the accompanying drawings.